1. Field of the Invention
The present invention relates to a data communication system and control method thereof, more specifically, to offset adjustment of a differential amplifier circuit within a data receiving apparatus.
2. Description of the Related Art
Recently, regulations related to vehicle safety have become tightened successively in Japan, the United States, and other countries. The tire pressure monitoring system (TPMS) is one known technique for improving the vehicle safety as disclosed in Japanese Laid Open Patent Application No. P2006-109105A (hereinafter, the '105 application), for example.
FIG. 1 is a schematic illustration showing the structure of the TPMS disclosed in the '105 application. The TPMS includes transmitter modules 111 installed within tires 100, sensor initiators 112, and a receiver module 113. The transmitter modules 111 each include sensors which measures the tire pressure and temperature. The receiver module 113 controls the respective transmitter modules 111 to obtain necessary information related to the tires 100 from the transmitter modules 111. The control of the transmitter modules 111 is achieved by feeding to the respective transmitter modules 111 command data which indicate operations to be done by the transmitter modules 111.
More specifically, the TPMS operates as follows: The receiver module 113 transmits command data to the transmitter modules 111 through the sensor initiators 112. The command data are transmitted with LF (Low Frequency) radio waves. Upon receiving the command data, the transmitter modules 111 measure the pressure and temperature of the respective tires by using the sensors. The transmitter modules 111 transmit measurement result data obtained by the sensors to the receiver module 113 with RF (Radio Frequency) radio waves. The receiver module 113 performs desired operations in response to the received measurement result data, for example, displays information regarding the tire pressure and the sensor on a display device 114.
One requirement is that the transmitter modules 111 receive the command data from the receiver module 113 with high accuracy.
FIG. 2 is a schematic diagram showing the structure of the transmitter modules 111. The transmitter modules 111 each include a microcomputer 120, an LF reception circuit 130, a coil antenna 140, and a reference level generation circuit 150. Provided within the microcomputer 120 are a CPU 122 and a memory 123 which are connected to each other through a bus line 121. The LF reception circuit 130 incorporates therein a damping resistor circuit 131, a comparator 132, a demodulator 133, and a switch SW. The command data are transmitted from the receiver module 113 to each transmitter module 111 with LF radio wave modulated with ASK (Amplitude Shift Keying) modulation. When the command data are transmitted with the LF radio wave, the coil antenna 40 generates an input voltage with LC resonance. The damping resistor circuit 131 includes a damping resistor R1 and the switch SW which are connected between the inputs of the comparator 132. The damping ratio of the input voltage is changeable by the switch SW. The input voltage generated by the coil antenna 140 is fed to the comparator 132. The output signal of the comparator 132 is sent to the demodulator 133 and demodulated thereby to reproduce the command data. The command data reproduced by the demodulator 133 are fed to the microcomputer 120. The microcomputer 120 executes commands incorporated in the reproduced command data.
The '105 application discloses that the comparator 132 within each transmitter module 111 incorporates a MOS transistor pair. Although comparators incorporating a bipolar transistor pair are well known in the art, the use of a bipolar transistor pair within a comparator undesirably requires additional manufacture steps for forming bipolar transistors in addition to manufacture steps for forming MOS transistors within logic circuits; logic circuits are usually comprised of MOS transistors. The use of a MOS transistor pair within the differential amplifier as disclosed in the '105 application effectively avoids the increase in the number of manufacture steps.
One issue of the use of a MOS transistor pair within the comparator 132 is that the characteristics of the two MOS transistors often differ from each other due to manufacture variations. This undesirably causes the offset of the comparator 132. For the case where the input voltage generated by the coil antenna 140 has an amplitude as small as 5 mV, for example, the offset of 5 mV makes it impossible to correctly detect the input voltage.
In order to address this issue, the transmitter modules 111 disclosed in the '105 application include an offset control circuit which adjusts the offset of the comparator 132. FIG. 3 is a block diagram showing details of the comparator 132 of the transmitter modules 111. As shown in FIG. 3, the comparator 132 includes a pair of differential transistors Tr11, Tr12 and an offset control circuit 134. The offset control circuit 134 controls the current supplied from the power supply line VDD to the differential transistor Tr11. The offset control circuit 134 provides adjustment of the balance between the currents through the differential transistors Tr11 and Tr12. This allows adjusting the offset of the comparator 132. Specifically, the offset control circuit 134 includes PMOS transistors (Tr3, Tr5 and Tr7) which function as offset switching switches, and PMOS transistors (Tr4, Tr6, and Tr8) for regulating the current through the differential transistor Tr11. When the offset switching switch PMOS transistors (Tr3, Tr5 and Tr7) are turned ON, currents are supplied to the differential transistor Tr11 from the corresponding current regulating PMOS transistors (Tr4, Tr6, and Tr8). When the number of current paths for supplying currents to the differential transistor Tr11 is increased, the total current amount through the differential transistor is increased (see FIG. 4). It should be noted that the offset control circuit 134 is designed to adjust the current through the differential transistor Tr11 so that the current through the differential transistor Tr11 is smaller than that through the differential transistor Tr12, when the same voltage is applied to the differential transistors Tr11 and Tr12 with all the offset select switches (Tr3, Tr5, Tr7) placed in the OFF state. When the number of the offset switching switches (Tr3, Tr5, Tr7) in the ON-state is increased to increase the total current amount through the differential transistor Tr11, the offset value of the comparator 132 is changed, resulting in that the output of the comparator 132 is switched from the high-level to the low-level at a certain operation point. When the number of the ON-state offset switching switches is adjusted so that the output of the comparator 132 is just switched from the high-level to the low-level, the offset value is set with highest sensitivity. The offset switching switch transistors (Tr3, Tr5, and Tr7) are switched in response to offset switch signals #1, #2 . . . #n received the microcomputer 120.
FIG. 5 is a flowchart showing an exemplary operation in adjusting the offset of the comparator 132. When the CPU 122 of the microcomputer 120 is started up, the microcomputer 120 turns on the switch SW and electrically connects the damping resistor R1 between input terminals of the comparator 132 to provide “low resistance”, before starting offset adjustment of the comparator 132. This results in that the voltage between the input terminals of the comparator 132 is sufficiently reduced at Step S101. The microcomputer 120 then sets the offset switching signal #1 to the low-level at Step S102. It should be noted that the offset switch signals. #1 to #n are low-active, and the corresponding offset switching switch transistors are turned on in response the to the pull-down of the offset switch signals #1 to #n. After the offset switching signal #1 is set to the low-level, the output (OUT) of the comparator 132 is monitored at Step S103. Then, the microcomputer 120 sets the offset switching signal #2 to the low-level at Step S104. This is followed by monitoring the output (OUT) of the comparator 132 at Step S105. The same goes for the remaining offset switch signals. Other offset switch signals are successively set to the low-level, followed by monitoring the output of the comparator 132. This process is repeated until the last offset switching signal #n is set to the low-level at Step S106. This is followed by determining the offset switch signal which causes the output of the comparator 132 to be just switched from the high-level to the low-level at Step S107. The state of the offset switch signals #1 to #n which just switch the output of the comparator 132 from the high-level to the low-level is the state where the offset is minimized. The state of the offset switch signals determined at Step S107 is saved in the memory 123. Then, the microcomputer 120 turns off the switch SW and thereby disconnects the damping resistor R1 from the input terminals of the comparator 132 at Step S108 to prohibit damping of the input voltage in normal operations.
The above described structure and operations of the transmitter module 111 allows minimizing the offset value of the comparator 132, allowing operating the transmitter module 111 with high sensitivity.
Another requirement for a tire pressure monitoring system is to reduce power consumption of the transmitter modules 111. The transmitter modules 111 of a TPMS are installed within the tires 100 so that the battery thereof cannot be exchanged for a long time. Thus, the power consumption of the transmitter modules 111 is desirably reduced in order to allow the battery to operate for a long time. Japanese Laid Open Patent Application No. P2006-107146A discloses that an intermittent operation control circuit for allowing the LF reception circuit to operate intermittently.
The technique disclosed in the '105 application, however, suffers from a drawback that the offset of the comparator 132 may be adjusted inappropriately, when the offset adjustment is performed while the antenna 140 receives radio wave. The microcomputer 120 is booted in response a startup signal from a startup control circuit, and then starts the offset adjustment. The offset adjustment is performed regardless of whether or not the antenna is receiving radio wave. When the offset adjustment is performed while the antenna 140 is receiving the radio wave, the offset value after the offset adjustment may be shifted from a desired value depending on the amplitude of the input voltage generated at the antenna 140. A detailed description is given of the reason thereof in the following.
The graph in the left region of FIG. 6 shows an example of the offset adjustment for the case where no LF radio wave is received, assuming that the offset value is changed by 1 mV when one offset switching switch is switched. It should be noted that the offset value is the difference between the voltage levels of the inverting and non-inverting inputs which causes the output of the comparator 132 is switched between the high-level and the low-level. When the number of turned-on offset switching switches is increased by one while the LF radio wave is not received, the offset value is increased by 1 mV. The case (1) shown in FIG. 6 is a case where the offset value is −1 mV with two offset switching switches turned on. For the case (1), the offset value is adjusted to exactly zero, by increasing the number of the turned-on offset switching switches up to three. When the number of the turned-on offset switching switches is increased up to four, the offset value is increased up to 1 mV. When the number of the turned-on offset switching switches is increased up to four, the output of the comparator is switched from the high-level to the low-level. Therefore, the state of the offset switch signals #1 to #n at this moment is determined as providing the minimum offset value at Step S107 of the procedure shown in FIG. 5. On the other hand, the cases (2) and (3) are cases where the offset value is not adjusted to exactly 0 even if the number of the turned-on offset switching switches is best adjusted. In the cases (2) and (3), the offset value cannot be adjusted to exactly 0 even if the number of turned-on offset switching switches is successively incremented one by one. However, the offset value certainly falls within a range between 0 and 1 mV with a certain number of turned-on offset switching switches. At Step S107, the state in which the offset value is within the range between 0 and 1 mV is determined as the state that provides the minimum offset value.
The right region of FIG. 6, on the other hand, shows the offset adjustment for the case where LF radio wave is received. It is assumed here that the potential difference between the inverting and non-inverting inputs of the comparator 132 generated by the radio wave is 2 mV at the maximum. In FIG. 6, the line (4) indicates the voltage level on the non-inverting input of the comparator 132. The line (5) corresponds to the state where the offset value is 1 mV, showing the value obtained by adding 1 mV to the voltage level on the inverting input terminal of the comparator. The line (6) corresponds to the state where the offset value is 2 mV, showing the value obtained by adding 2 mV to the voltage level on the inverting input of the comparator. The line (5) goes below the line (4) in the hatched areas. This implies that the voltage applied to the non-inverting input exceeds the value obtained by adding 1 mV to the voltage level on the inverting input. In such state, the output of the comparator 132 is pulled up to the high-level. Therefore, the output of the comparator 132 is misjudged as the high-level at timings indicated by the hatched areas, although the offset value is actually a positive value. In this case, the state with the offset value of +1 mV is not determined as offering the minimum offset value at Step S107 shown in FIG. 5. Such a phenomenon where the output of the comparator 132 which is actually the low-level is misjudged as the high-level may occur in the range where the offset value is +2 mV (indicated by the line (6)) or less. Therefore, an adjustment error of about 2 mV may be generated at the maximum. This phenomenon is enhanced as the amplitude of the input voltage generated by the radio wave is increased. This implies that the radio wave cannot be demodulated even if the radio wave provides the input voltage with an amplitude of 2 mV, necessitating the input of radio wave with a larger amplitude.
As thus discussed, the technique disclosed in the '105 application requires adjusting the offset value under a state in which the radio wave is not received, in order to accurately set the offset value.
It is therefore desired to provide a technique for performing offset adjustment accurately whether or not the antenna is receiving radio wave.